Principal ASIC Design Engineer

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not.

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

The experience expected from applicants, as well as additional skills and qualifications needed for this job are listed below.

PRINCIPAL DIGITAL ASIC DESIGN ENGINEER

OVERVIEW :

This is a principal digital ASIC design role in the development of broadband satellite modem hardware solutions. This position includes significant responsibilities in one or more of the following areas : requirements and specifications, micro-architectural definition, digital design (RTL) and verification, synthesis, static timing analysis, and power estimation and optimization.

Project deliverables may include specification documents, micro-architecture designs, RTL code, simulation models, test benches, gate-level netlists, timing constraints, UPF files, and associated documentation and additional collateral.

As a principal digital ASIC designer, you will be responsible for all aspects of digital ASIC design focusing on RTL design, verification, logic synthesis, and timing analysis.

You will design digital signal processing (DSP) data paths and control systems for advanced mixed analog / digital integrated circuits in System Verilog.

Job functions also include verification and debugging for digital modules through simulation, and development of functional test cases.

Design optimization and tradeoffs for balancing performance, power, and area is required.

RESPONSIBILITIES :

• RTL design of digital circuits using hardware description languages such as Verilog and System Verilog.
• Logic synthesis using Synopsys Design Compiler.
• Estimating and scheduling your work so that progress can be managed by our in-house program management group.
• Documenting high-level description of designs and requirements for signal processing subsystems.
• Writing functional test cases to verify and debug digital designs.
• Writing scripts using languages such as Tcl and PERL to achieve higher performance and improve productivity through automation.
• A self-starter with the ability to manage your own time effectively, and the ability to work well in a diverse team environment.

BASIC QUALIFICATIONS :

• Bachelor of Science degree in electrical engineering, computer science or computer engineering.
• 12+ years of work experience.
• 3+ years of experience in developing automated, self-checking Test benches.
• 5+ years of experience in STA, timing constraints and closure on high speed, low power designs.
• 3+ years of experience in scripting languages (perl, tcl, make or shell).

PREFERRED SKILLS AND EXPERIENCE :

• Masters of Science in electrical engineering, computer science or computer engineering.
• Programming proficiency using Verilog / System Verilog.
• Familiar with ASIC design methodology / flows / checks for digital designs.
• Problem solving skills with appropriate attention to detail.
• Experience with synthesis tool and flow to generate high quality netlists for various blocks.
• Good coordination and problem solving skills and ability to meet tough goals under high pressure.
• Self-directed and motivated to be successful in a fast paced environment.
• Strong interpersonal, written and verbal communication skills.
• Experience with revision control systems such as subversion, ClearCase or GIT.
• Knowledge of wireless communications systems and standards, including 4G LTE (FDD / TDD). Experience in modem design and verification.
• Digital design and verification, digital communications, and signal processing.
• ASIC synthesis, formal verification, gate level simulation, static timing analysis, UPF simulations, and / or power estimation.
• Experience / knowledge in the architecture / RTL design of signal processing wireless protocols including 802.11a / b / g / n / ac or hands-on experience in any of one of LTE / WiMAX / 4G / Gigabit DSP preferable.
• Experience with Synopsys synthesis and timing analysis tools.
• Knowledge of wireless communications systems and standards, including LTE (FDD / TDD) and UMTS. Experience in modem design and verification.
• Experience with revision control systems such as Subversion or GIT.
• Experience with scripting languages such as TCL, Python, or Perl.
• Experience in the design and implementation of high speed forward error correction (FEC) codecs, such as Turbo Codes, LDPC, convolutional, and Reed-Solomon codecs.
• Experience with VCS, Verdi, and Spyglass.
• Experience with DPI-C, System Verilog, UVM.
• Experience with C / C++, Python, Matlab and / or other simulation and modeling tools / languages.
• Experience in PCIe, Ethernet and DDR interfaces and understand their I / O protocols.
• Experience in AMBA bus architecture and its protocols.
• Experience in Wi-Fi and / or other wireless networking. Experience in 802.3 and network processing.

ADDITIONAL REQUIREMENTS :

Must be available to work extended hours and weekends as needed.

ITAR REQUIREMENTS :

To conform to U.S. Government space technology export regulations, applicant must be a U.S. citizen, lawful permanent resident of the U.

S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin / ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other

J-18808-Ljbffr