FPGA Design Engineer

Description

Preferred Qualifications

KLA is bringing the semiconductor industry to the Midwest! We need a FPGA Programming Design Engineer on our growing Ann Arbor team to assist in developing product equipment, test centers, software, and AI algorithms that power innovative capabilities that KLA is recognized for.

By joining our hard-working KLA team in Ann Arbor, you’ll enjoy an incredible career with encouraging colleagues in a spectacular place to live.

Main job responsibilities in the KLA Design Process include :

Participate in all phases of FPGA design flow - from concept to wafer inspection tool integration.

Able to derive FPGA design requirements from system requirements.

Responsible for RTL design and verification, as well as hardware bring-up.

Implement logic / control blocks, including custom filters, DSP / image processing blocks, a high-speed image data path, and a processor and memory interface to support real-time processing.

Optimize FPGA designs for the area, speed, and power to meet system requirements; analyze architectural trade-offs and validate for system sample rate and latency.

Verify DSP / image processing blocks against Python / MATLAB models and collaborate with systems engineers.

Run implementation tools, such as Xilinx Vivado and Intel Quartus; perform timing closure for your designs.

Bring up FPGA design in the lab with necessary lab equipment and complete validation of the design.

Collaborate with software engineers to integrate the design into wafer Inspection tools.

Contribute to all phases of hardware development, including creating design documents, reviewing schematics, bringing up new hardware, and defining / overseeing / performing unit and system tests.

Validate FPGA design for manufacturing release.

Qualifications

Experience designing DSP and / or image processing datapath

Experience in working with FPGAs

Some experience designing hardware (schematic entry, layout, etc.) is a plus

Strong programming and scripting skills : MATLAB, Python, C / C++, Perl, Tcl

Understanding of clock domain crossing (CDC) techniques

Experience in FPGAs, evaluation boards, and knowledge of FPGA design flow

Understanding industry-standard interfaces, protocols, and architectures : PCIe, Ethernet, DDR, etc.

Experience in developing automated, self-checking test benches and / or UVM

Experience in EDA tools such as simulators (e.g., Questa), and FPGA tools (e.g., Vivado, Quartus)

Knowledge of timing closure techniques for high-speed design

Minimum Qualifications

Bachelor’s degree with +5 years’ work experience, OR Master’s degree with +3 years’ work experience, OR PhD with 0 years’ work experience

The company offers a total rewards package that is competitive and comprehensive including but not limited to the following : medical, dental, vision, life, and other voluntary benefits, 401(K) including company matching, employee stock purchase program (ESPP), student debt assistance, tuition reimbursement program, development and career growth opportunities and programs, financial planning benefits, wellness benefits including an employee assistance program (EAP), paid time off and paid company holidays, and family care and bonding leave.

KLA is proud to be an Equal Opportunity Employer. We do not discriminate on the basis of race, religion, color, national origin, sex, gender identity, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other status protected by applicable law.

We will ensure that qualified individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment.