Design Verification Engineer
Role Title : Emulation Methodology Engineer
Location : Austin, TX
Duration : 6+ months contract
Job Description :
- Develop and drive improvements using the latest emulation technology from industry.
- Support emulation methodology & emulations tools (Veloce, Palladium & ZeBu) as part of central methodology team.
- Creating App Notes & Articles for Frequently Asked questions
- Develop emulation tools, workflows and infrastructure in collaboration with RTL, verification, validation and SW teams for productivity during debug, runtime, and data analysis of results from emulation runs.
- Develop emulation validation components for validation efficiency in testing, debug and automation.
- Bring up and debug PCIe, DDR and generic SOC interfaces.
- Integrate and bring-up 3rd party accelerate verification IPs.
- Identify solutions for emulation challenges and provide methodology.
- Bring up ML / AI applications in emulation
Required Skills :
- Good Experience (5+ years) with Emulation based Verification using : Cadence Palladium, Synopsys Zebu or Mentor Veloce
- Solid programming skills in C / C++, Verilog, System Verilog, UVM, assembly, Perl / Python.
- Proficient in debugging complex SOC, GPU or CPU core designs
- Experience in triaging regressions, debugging, and resolving down to RTL or Testbench issues.
- Ability to develop and enhance emulations transactors
- Experience with UPF and Power Estimation based Emulation is plus
- Potential to be a contract-to-hire position
- If the contractor expects to end their assignment early, a one month notice is preferred to allow time to identify a replacement and for knowledge transfer
Thanks & Regards..,
Shaik Hyder,
hyder@infobahnsw.com
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