ASIC Digital Design, Principal Engineer

Principal DDR / HBM PHY Architect

48946BR

CANADA - Ontario - Markham, CANADA - Ontario - Mississauga, CANADA - Ontario - Nepean, USA - California - Mountain View / Sunnyvale, USA - Massachusetts - Boxborough

Job Description and Requirements

We're looking for a senior DDR / HBM PHY architect to join the team.

Does this sound like a good role for you?

In this position, you would be part of a team that plans and executes the design for the next-generation DDR and HBM PHYs in the Synopsys IP portfolio.

The job entails understanding industry trends through participation in standards bodies, evaluating ideas, drafting specifications, and enabling the design team to put your ideas into silicon.

You'd leverage your understanding of computer architecture, mixed-signal design, off-chip signaling, RTL development, design-for-test, and logical verification to create leading-edge products.

Supporting Synopsys' customers is also a significant part of the role. You will join a collaborative, multi-person engineering team engaged in similar activities on related DDR and HBM PHY development projects.

Job Responsibilities :

Understands marketing and customer desires for Synopsys' DDR and HBM PHY interface performance and functionality

Translates those desires into a set of product design features and functions

Generates the functional description for the product, creating specifications describing the interface components, operation, structure, and behavioral parameters

Optimizes the design for performance, power, and area

Interacts and communicates with design teams performing logical design, logical verification, analog circuit design and verification, and layout design

Supports customers in their implementation of the product

Tracks industry developments through standards committees, representing Synopsys in these committees

Key Qualifications and Experience :

Understands high-speed interface principles, such as mixed-signal design and off-chip signaling

Skilled in generating and supporting documentation through written specifications, and communicating those specifications within a design team and to external customers

Well-versed in RTL logic design, simulation, test planning, and verification of complex integrated circuit components

Knowledgeable in design-for-test, timing analysis, power analysis, behavioral modeling, and synthesis constraints

Able to work across a multi-site team to communicate ideas, understand problems, and find solutions to create a leading-edge design.

Skilled in troubleshooting and debug of mixed-signal interfaces

Possesses a minimum of 10+ years of related experience.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

The base salary range across the U.S. for this role is between $150,000-$224,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses.

Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education.

Your recruiter can share more specific details on the total rewards package upon request.

Job Category

Engineering

Country

United States

Job Subcategory

ASIC Digital Design

Hire Type

Employee

Base Salary Range

$150,000-$224,000

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