Summary :
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly.
Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here.
The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it.
Join us to help deliver groundbreaking Apple products!Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level physical design.
Key Qualifications :
Minimum BS and 3+ years of relevant industry experienceSolid electrical engineering fundamentals in digital circuits, timing / power concepts, and basics of logic designExperienced in using industry standard logic Synthesis, PnR, STA and Power analysis tools along with floor-planing, pin-placement and timing budgeting knowledge Familiar with programming and scripting (Perl, TCL) with strong fundamentalsAbility to work well in a team, self-motivated and excellent communication skills
Description :
As a CPU Physical Design Engineer you will drive or participate in the following : - Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious PPA goals - Will be responsible for block-level physical design delivery along with closure of backend flows, electrical requirements and improving silicon yield - Will work closely with internal CAD and PD methodology teams on industry standard synthesis / PNR tool features and optimizations and their adoption in CPU design - Will work with x-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability - Will work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA
Additional Requirements :
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