About HCLTech :
HCLTech is a global technology company, home to 221,000+ people across 60 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products.
We work with clients across all major verticals, providing industry solutions for Engineering Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services.
To learn how we can supercharge progress for you, visit
Job Summary :
As a Senior DfX Design Engineer, you will be responsible for driving Design for Excellence (DfX) methodologies specifically in the context of System-on-Chip (SoC) designs.
You will work closely with cross-functional teams to ensure that our SoC products are designed with manufacturability, testability, reliability, and cost-efficiency in mind from the early stages of development.
Key Responsibilities :
DfX Integration : Lead the integration of DfX principles (Design for Testability, Manufacturability, Reliability, etc.
into SoC design flows, ensuring that all aspects of the chip design are optimized for production and lifecycle management.
- Methodology Development : Develop and refine DfX methodologies for SoC designs, including the creation of guidelines, checklists, and best practices that can be applied across multiple projects.
- Design Reviews : Conduct thorough design reviews focused on DfX, providing actionable feedback and recommendations to design teams to enhance SoC quality and performance.
- Collaboration : Work collaboratively with design, verification, physical implementation, manufacturing, and test engineering teams to identify and address DfX challenges early in the design cycle.
- Testability and Yield Optimization : Drive the design for testability (DfT) strategies, including scan insertion, Built-In Self-Test (BIST), and boundary scan, to improve yield and reduce test costs.
- Reliability and Robustness : Implement design strategies to enhance the reliability and robustness of SoC products, including techniques for dealing with process variations, aging effects, and environmental stresses.
- Cost Reduction : Analyze and optimize design choices to reduce overall chip costs, considering factors such as die size, power consumption, and material usage.
- Risk Management : Identify potential design risks and develop mitigation strategies to ensure that SoC products meet all necessary standards and performance criteria.
- Mentorship : Provide technical leadership and mentorship to junior engineers, fostering a culture of innovation and continuous improvement within the DfX discipline.
Qualifications :
- Education : Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience : Minimum of 8-12 years of experience in semiconductor design, with a strong focus on SoC DfX methodologies.
- Technical Skills :
- Deep understanding of DfX principles, particularly in Design for Testability (DfT), Design for Manufacturability (DfM), and Design for Reliability (DfR) in the context of SoC.
- Proficiency in EDA tools and methodologies used in SoC design, including simulation, synthesis, and verification tools.
- Experience with test strategies such as ATPG (Automatic Test Pattern Generation), scan chains, and BIST.
- Familiarity with yield analysis, reliability modeling, and failure analysis techniques.
- Knowledge of semiconductor manufacturing processes and challenges related to advanced technology nodes.