A RISC-V Start Up is seeking SOC Verification - Emulation engineers to work on projects ranging from subsystem level to multi-chip level, covering all aspects of emulation including functional, performance, microarchitecture, and debugging.
Role Overview
As an SOC Verification - Emulation Engineer, you will develop Emulation and FPGA-based prototyping systems to support our SOC projects.
You will collaborate with architecture, design, verification, and software / firmware teams to develop emulation models and capabilities for various use cases such as functional verification, performance testing, software / firmware bring-up, running realistic workloads, power estimation, hybrid-simulation, and post-silicon debugging.
Your responsibilities may include developing and debugging emulation flows, designing testbenches, monitors or transactors, synthesizing RTL for emulation, and creating RTL collateral for emulation.
Key Responsibilities
- Create and support emulation models from RTL and drive SOC bring-up on emulation platforms.
- Debug test failures and resolve simulation / emulation mismatches.
- Develop compile and runtime flows for various emulation use cases including functional verification, hybrid simulation, post-silicon debugging, power estimation, and software / firmware enablement.
- Develop capabilities to run tests on emulators and assist in bring-up processes from RTL prototyping through post-silicon validation.
- Collaborate with tool vendors to drive requirements and resolve tool issues.
- Contribute to methodology and automation improvements to enhance emulation efficiency and value.
Requirements
- Deep understanding of digital logic design, CPU / SOC architecture, microarchitecture, and industry-standard interfaces and memory subsystems.
- Proficient in Verilog / SystemVerilog.
- Proficient in C / C++.
- Familiarity with verification methodologies and tools such as simulators, waveform viewers, and build / run automation.
- Experience with emulation tools such as Palladium, Zebu, Veloce, Protium, or HAPS.
- Experience with QEmu or other software simulators is a plus.
- Experience in simulation acceleration using transactors or vendor-provided accelerated verification IP is a plus.
- Skilled in performance analysis and debugging techniques.
- Proficiency in scripting languages such as Python or TCL is a plus.
- Excellent problem-solving skills, strong written and verbal communication skills, excellent organizational skills, and high self-motivation.
- Ability to work effectively in a team and be productive under aggressive schedules.
Education and Experience
- PhD, Master’s Degree, or Bachelor’s Degree in a technical subject area.
- Apply now to be a part of a dynamic team driving the future of SOC emulation technology!
Graphics Design Verification Engineer
The Graphics Verification Engineer will be responsible for the pre-silicon RTL verification of blocks in low power embedded graphics cores. Perform unit-level, subsystem, and top verification for logic blocks in graphics processing unit (GPU) designs. Work closely with design & micro-architecture te...
Senior IP Design Verification Engineer
Responsible for Design Verification of complex IP using latest DV methodologies. Define and execute Formal verification plan to stress the design. Years of hands on experience in Design Verification (DV) on Complex IP used in subsystems. Experienced in all latest DV methodologies: Formal Verificatio...
Cellular SOC Design Verification Engineer
As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing innovative Cellular SoCs! This position requires someone comfortable will all areas of SoC design verification engineering. Arch...
Design Verification Engineer
Austin Frasers manufacturing client are looking for a Design Verification Engineer to join them on an initial 12 month contract, ideally the candidate will be local to Austin,TX for on site working but they will consider top tier candidates who have a strong remote set up as well. ...
Design Verification Engineer
Define design verification methodology and test benches. Work with design and micro architecture teams to understand performance and functional goals of the design. Create software to verify architecture and functionality of pre-silicon hardware designs. Maintain deliverables to align with project g...
Design Verification Engineer
Working closely with Micron's global design teams to contribute to the success of the design team by applying verification tools and techniques, providing verification status and summaries to specific designs as needed. Participate in developing digital/analog mix-signal verification methodology for...
Senior Design Verification Engineer - Memory Subsystem Verification, C++, SystemVerilog
Are you looking to take on and tackle advanced engineering challenges? We are looking for open minded, flexible, innovative, and creative Engineers looking to join a new team to develop an end to end verification solution from IP/subsystem verification through advanced technics, including BIOS verif...
Senior SoC Design Verification Engineer
Senior SoC Design Verification Engineer. Experience with full verification flow including coverage closure. System verification (C based) experience. ...
Senior Design Verification Engineer - Memory Subsystem Verification, C++, SystemVerilog
THE PERSON: Are you looking to take on and tackle advanced engineering challenges? We are looking for open minded, flexible, innovative, and creative Engineers looking to join a new team to develop an end to end verification solution from IP/subsystem verification through advanced technics, includin...
Staff Design Verification Engineer
As a Staff Design Verification Engineer youwill play a pivotal role in ensuring the functionality andperformance of our custom mixedsignal ASICs. MS or PhD inElectrical Engineering or ComputerEngineering. Innovate the Futureof MixedSignal Processing: Join a WorldClass VerificationTeam. Collaborate w...