Search jobs > San Jose, CA > Implementation lead

Senior/Lead RTL to GDSII Digital Implementation

Cadence Design Systems, Inc.
SAN JOSE
Full-time

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Key Responsibilities

Hands-on work with Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Synthesis, Place and Route, Design Closure, and timing / power signoff, RTL to GDSII.

Lead technical campaigns and strategies in the RTL to GDSII digital implementation space.

Aggressively push Power, Performance, and Area (PPA)

Deliver technical presentations and lead discussions internally and with customers.

Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements with high quality.

Support execution on critical customer flagship product tape outs.

Amend and augment the flow as needed using Tcl and / or other programming skills to meet objectives and improve results / flows.

Job Requirements

Minimum

8+ years industry experience plus MS degree Computer Science / Engineering, Electrical, Engineering, or related field.

Prior experience with IC digital implementation flows and backend EDA tools including Synthesis, Place and Route, IR Drop, backend design timing and power closure, RTL to GDSII.

Experience in scripting in Perl / Tcl / Python to automate and implement process improvement is a must.

Floor planning and power planning for System-on-Chip (SoC) designs with low power

Prior experience with IC digital implementation flows including Synthesis, DFT, and Logical Equivalence Checking

Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required.

Good hands-on experience of Floorplanning, Place and Route, Timing analysis and Sign-off, preferable with CDNS tools suite

Advanced clock tree synthesis techniques including SoC Clock Distribution, Clock Mesh, H-Tree

Multiple design closure including Timing, DRC, LVS, and EMIR preferred.

Experience with advanced technology nodes including Sub 5nm and below.

Develop, debug, and optimize various aspects of design flows for SoC’s to achieve best Power, Performance and Area (PPA)

Strong customer-facing communication and problem-solving skills

Strong personal drive for continuous learning and expanding professional skillsets.

Strong verbal, written, and customer communication skills.

Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, and / or Voltus is highly desired.

LI-MA1

We’re doing work that matters. Help us solve what others can’t.

30+ days ago
Related jobs
Cadence Design Systems, Inc.
San Jose, California

Hands-on work with Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff, RTL to GDSII. Lead technical campaigns and strategies in the RTL to GDSII digital implementation space. Prior experie...

Promoted
Uber
Sunnyvale, California

The Global Digital Lead plays a critical role executing high-impact Uber Delivery wide digital led transformation initiative and continuously improving digital experience for our Commercial teams, ensuring business values are delivered to the organization. As a Quote to Cash Digital Lead, you will b...

Cadence Design Systems, Inc.
San Jose, California

The ideal candidate will have at least 5 plus years of actual work experience as well as a thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project devel...

Grant Thornton
San Jose, California

Grant Thornton is seeking a Tax Digital Consulting - Enterprise Tax Engine Implementation - Indirect Tax Senior Manager to join our team in Houston, TX. Working closely with clients to gather feedback on their issues and translate into Grant Thornton service offerings that support their overall tax ...

Cadence Design Systems, Inc.
San Jose, California

As an expert Digital Implementation and Signoff Field Applications Engineering (AE), you will work side-by-side with our leading edge customers. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in nanometer design, unlock unique expertis...

Advanced Micro Devices, Inc
Santa Clara, California

Working with customers and consumers to understand feature requirements and translate them into implementable specs Definition of RTL architecture, microarchitecture, and design implementation of memory PHYs Documentation of RTL architecture and micro-architecture RTL coding, code reviews and debug ...

Lam Research
Fremont, California

Digital Transformation, Senior Manager of NPI is a unique opportunity to transform a market leading semiconductor company to scale for future growth at an unprecedented time in our industry. Transform the way Lam uses connected digital tools and systems to empower our employees with better tools and...

Western Digital
Milpitas, California

From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future. Extensive experience...

CADENCE US
San Jose, California

Provide technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff. Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements. At Cadence, w...

ACL Digital
San Jose, California

ACL Digital - 2890 Zanker Road, Suite 200, San Jose, CA 95134. ...