Seeking FPGA RTL to be part of a small, multidisciplinary hardware engineering team in the role of designing logic and closing timing constraints for high-speed interfaces and complex video processing algorithms.
In this position you will write documentation, work with the hardware team to determine FPGA systms architecture, Implement IP cores and simulation in VHDL-2008, and perform in-circuit programming and debugging.
Requirement :
- Minimum 3 years experience in FPGA RTL design
- VHDL-2008
- Xilinx Vivado, Lattice Diamond
- RTL circuit design and timing closure
- High-speed interfaces
- MIPI CSI-2, subLVDS
- JEDEC memory interfaces (DDRx SDRAM, NAND flash, etc)
- PCIe (utilization of hard IP)
- Signal & video processing and arithmetic in FPGAs
- DMA interfaces for ARM microprocessors, etc
- Git and GitHub repository
FPGA RTL Engineer
Seeking FPGA RTL to be part of a small, multidisciplinary hardware engineering team in the role of designing logic and closing timing constraints for high-speed interfaces and complex video processing algorithms. Minimum 3 years experience in FPGA RTL design. In this position you will write document...
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