Position : Design Verification Engineer
Location : San Jose / Austin (Onsite / Hybrid)
Position Overview :
- 5+ years of relevant experience in Design Verification.
- Experience with System Verilog and UVM is a must.
- Strong experience in testbench development such as UVM methodology.
- Knowledge of GPU, experience with Shader, Texture, or Memory System a plus.
Responsibilities :
- Develop Scalable SystemVerilog / UVM testbenches for unit level and / or Cluster level verification.
- Triage regression failures and make testbench updates.
- Generate and run Testcases on logic simulation models.
- Closely work with Architects and RTL designers.
- Drive Functional Coverage and Code coverage to closure.
Education :
Bachelors Degree in related field.
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