R&D Engineering, Sr Manager

Senior Manager, RTL Engineering

49828BR

USA - Texas - Austin

Job Description and Requirements

We Are :

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You Are :

You are a seasoned professional with a passion for digital design and a knack for leadership. With over 8 years of industry experience, you bring a wealth of knowledge in Verilog and System Verilog, coupled with hands-on experience in RTL logic design, debug, and verification.

Your ability to communicate effectively and lead a team is unparalleled. You thrive in a collaborative environment and are always eager to learn and adapt to new challenges.

You understand the intricacies of digital microarchitecture and have a keen eye for optimizing performance, power, and area.

Your technical prowess is complemented by your strategic thinking, making you an invaluable asset to any team.

What You'll Be Doing :

• Leading the Front-End design team with technical leadership and management.
• Engaging in hands-on digital microarchitecture definition and documentation.
• Understanding and working with digital logic and RTL circuit representation.
• Designing, debugging, and verifying RTL logic for optimal timing, area, and power.
• Collaborating with other design functionalities for end-to-end IP productization.
• Assisting in characterizing the IP and contributing to lab bring up.

The Impact You Will Have :

• Driving the successful development and integration of digital hardware IP crucial for SLM (Silicon Lifecyle Management) sensors.
• Enhancing the performance, power efficiency, and reliability of semiconductor products.
• Reducing the time to market for differentiated products with reduced risk.
• Providing technical leadership that fosters innovation and excellence within the team.
• Contributing to the overall success of Synopsys' Silicon Lifecycle Management business.
• Shaping the future of technology through continuous improvement and cutting-edge design.

What You'll Need :

• Proven team leadership and exceptional communication skills.
• Deep expertise in Verilog and System Verilog with experience in behavioral and structural RTL coding.
• Strong knowledge of digital logic and RTL circuit representation.
• Experience in Place and Route, Design Reuse, and / or Physical Design or Analog Design is a plus.
• 8+ years of industry experience in digital design and verification.

Who You Are :

• A collaborative team player who thrives in a fast-paced environment.
• An innovative thinker with a strategic mindset and problem-solving skills.
• An effective communicator who can articulate complex technical concepts clearly.
• A detail-oriented professional with a commitment to excellence.
• A proactive leader who can inspire and guide a team to success.

The Team You'll Be A Part Of :

The Digital R&D team within the HDG (Hardware Development group) is chartered with developing digital hardware IP that are crucial components of the SLM sensors.

Our team is dedicated to pushing the boundaries of technology and innovation, creating solutions that enhance the lifecycle of semiconductors.

Join us and be a part of a dynamic team that is shaping the future of technology.

Rewards and Benefits :

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity :

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

LI-DP1

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Job Category

Engineering

Country

United States

Job Subcategory

R&D Engineering

Hire Type

Employee

Base Salary Range

$174,000 - $260,000