Digital Verification Lead - Perm - San Francisco/Silicon Valley OR Pittsburgh

At a glance :

• Onsite in San Francisco Bay Area / Silicon Valley, CA -or- Pittsburgh, PA
• Full-time position
• Starting $200k
• 3-step interview process
• Needed ASAP

Top skills :

• The ability to develop and guide the overall Digital Verification Strategy from conception to execution
• Experience working with outside firms / agencies to augment Digital Verification requirements
• Communication is EXTREMELY important! The ability to communicate with internal (CTO) and external teams regarding the Digital Verification Strategy

Official job description :

If you are a Digital Verification (DV) Lead specializing in SoC verification who wants to influence the transformation of the next evolution of computing, we would like to talk to you.

We are seeking an experienced engineer who will lead the coordination of our digital verification efforts for our first-generation product.

The DV Lead will develop detailed specifications and a test plan for ensuring a high-quality SoC. They will be responsible for the overall execution of this test plan by working closely with not only the Engineering teams but also 3rd-party service providers.

Thereafter, the DV Lead will help shape our internal processes for building robust and verified designs, including the company’s second product line, which will scale computing performance and capability, while improving energy efficiency.

This is a unique opportunity to get in at the ground level and have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.

Join our team and help us shape the future of computing at the edge and beyond! This job can be located in Silicon Valley / San Francisco Bay Area, or Pittsburgh PA.

Key Responsibilities

• Develop SoC specifications in collaboration with the design team that describe the functionality of various chip components, including the expected inputs, outputs, and state machines.
• Write digital SoC verification plans and scope digital verification development tasks, including the development of functional coverage groups.
• Develop a reusable test bench and portable test components that can be used to verify both full systems and system components.
• Manage external 3rd-party digital verification service providers to ensure deadlines are met and project plans are adhered to.
• Act as liaison between external service providers and the engineering teams to ensure requirements are met, troubleshoot as needed, and facilitate regular meetings.
• Collect, collate, analyze, and present coverage reports. Work closely with digital designers to determine a strategy to close any coverage gaps.
• Support running gate-level simulations as part of design signoff.
• Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions.
• Assist in developing internal processes and frameworks to improve code quality, coverage, and correctness.

Required Qualifications & Experience

• 4+ years of Digital SoC Verification project management experience with specific experience managing small external teams of verification engineers and / or vendors.
• Experience writing and maintaining System Verilog test benches and test components.
• Bachelor’s degree in Engineering or a related field is required; Master’s degree or PhD is a plus.
• Minimum 5+ years of experience in design verification.
• Experience writing custom and reusable verification infrastructure (drivers, monitors, agents, and models).
• Well-versed in coverage-driven, constrained random verification, including coverage analysis and coverage closure.
• Ability to analyze performance and correctness regressions to determine their root cause.
• Experience with script development for work automation, preferably experience with Python.
• Knowledge of computer architecture, processor design and implementation, hardware and software engineering, and software development toolchains is a plus.
• Knowledge of UVM / OVM or equivalent portable verification methodologies, as well as IEEE-1801 (UPF) simulation flows is a plus.
• Offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, flexibility, and more! We are committed to personal and professional development and strive to grow together as people and as a company.
1 day ago