Description : Architect block and full-chip verification environments using HVLs and constrained random
techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA
Develop test plans and coverage metrics from specifications and write block and chip-level
tests in C,SV,UVM
Debug RTL and Gate simulations and work with design engineers to verify fixes.
Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.
Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.
Evaluate latest verification methodologies and develop scripts etc. to automate verification
flows.
At KAYGEN, we are always looking for dynamic, talented and experienced individuals. We invite you to join our team of talented IT professionals, consulting at client locations across the globe.
Our culture is team-orientated; we strive to stand by our core values of respect, honesty and integrity. Our team of experienced staffing experts will work with you to find you the best opportunity.
Wireless SoC Design Verification Engineer
As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state of the art Wireless SoCs! This position requires someone comfortable with all areas of SoC design verification engineering...
Design Verification Engineers (SoC-5, PCIe-5)
Role: Design Verification Engineers (SoC-5, PCIe-5). Job Title: Design Verification Engineers. Key Skills: UVM, SoC, PCIe, High Bandwidth memory, Emulation (Zebu or Palladium). Debug RTL and Gate simulations and work with design engineers to verify fixes. ...
Cellular SOC Design Verification Engineer
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Design Verification Engineers (SoC-5, PCIe-5)
Debug RTL and Gate simulations and work with design engineers to verify fixes. Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup. Description : Architect block and full-chip verification environments using HVLs and constrained random. SOCs with embedded CPUs...
Verification Engineer/ASIC RTL / SoC Design Engineer
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Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. Job Title: ASIC/SoC Design Verification Engineer Position Type: Full-Time / On-Site Location: Fremont, CA Salary Range / Rate: $110,000 - $300,000...
Soc Design Verification Engineer
Create verification content including testplans, test bench components, directed and constrained random tests, and functional coverage. Execute testplans to fully verify SoC component blocks. Knowledge of high-level verification flow methodology (testplan development, constrained random test generat...
Hardware Design Verification and Performance Modeling Engineers
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Cellular SOC Design Verification Engineer
As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing innovative Cellular SoCs! This position requires someone comfortable will all areas of SoC design verification engineering. By c...
Electrical Design Engineer (FPGA Design, PCB Design) (E)
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