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Design Verification Engineers (SoC-5, PCIe-5)

Kaygen
San Jose, CA, US
Full-time

Description : Architect block and full-chip verification environments using HVLs and constrained random

techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA

Develop test plans and coverage metrics from specifications and write block and chip-level

tests in C,SV,UVM

Debug RTL and Gate simulations and work with design engineers to verify fixes.

Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.

Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.

Evaluate latest verification methodologies and develop scripts etc. to automate verification

flows.

At KAYGEN, we are always looking for dynamic, talented and experienced individuals. We invite you to join our team of talented IT professionals, consulting at client locations across the globe.

Our culture is team-orientated; we strive to stand by our core values of respect, honesty and integrity. Our team of experienced staffing experts will work with you to find you the best opportunity.

30+ days ago
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