Senior DFT Engineer, Hardware Compute Group

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers.

We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa.

We want you to help us build on the success of our first generation of ML accelerator at edge.

Work hard. Have Fun. Make history.

At Amazon, DFT (Design-for-Testability) is a multi-faceted job that involves architecture definition, logic design, verification, test patterns generation, chip bring-up and more.

As a DFT Engineer, you will impact and see the device through its entire lifecycle, from definition stage to high volume production.

You will be working in close collaboration with multiple VLSI engineering groups including design, verification, backend, test, reliability and more.

As part of the SOC DFT team, you will :

• Develop and implement DFT architecture
• Design and verify DFT logic and components
• Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon
• Review sign-off level timing closure using static timing analysis of various DFT modes
• Contribute to wafer probe testing, ATE testing, silicon bring-up, diagnosis and support for physical failure analysis
• Take high volume chips to production with high coverage ATE test program

BASIC QUALIFICATIONS

• BS degree in Computer Engineering / Electrical Engineering.
• 7+ years in semiconductor companies as a Sr. DFT Engineer.
• Top level DFT architecture definition experience.
• Scan insertion tools and methodologies for Core and IP logics.
• MBIST, BISR, BIHR insertion tools and methodologies - Experience with both regular and shared bus MBIST architecture / flow.
• Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation.
• Experience in writing verilog / system verilog RTL related to DFT logic design.
• Experience in Chip level DFT verification methodology and flow.
• Perform SOC / IP DFT Gate-level simulations.
• Static timing analysis and DFT related timing constraints debug and closure.
• Scripting (Perl / Tcl)
• Experience in bringing up ATE test programs and taking complex SOC / ASIC to production.
• Experience in working with product & test engineers in taking chips from design to production.

PREFERRED QUALIFICATIONS

• MS or PhD degree in Computer Engineering / Electrical Engineering or related field.
• Excellent communication skills. Should be able to well communicate and establish relations with internal customers .
• Experience working with Manufacturing and equipment vendors.
• Energetic, self-motivated.
• Pro-active, oriented on execution.
• Attentive to details and quality.
• Team player, with the ability to work in a rapidly evolving / changing environment.
• Ability to work well with overseas partners and IP providers.
30+ days ago