As a ASIC Design Engineer, you work with a team creating hardware accelerator IP to be deployed in a range of Amazon devices.
You will develop hardware IP to accelerate applications in machine learning, computer vision and robotics. You will work closely with scientists, SoC Architects, software and verification to develop IP that meets the power, performance and area goals for Amazon devices.
You will help define the processes, methods and tools for design and implementation of large complex IP blocks.
In this role you will :
- Micro-architect and design hardware accelerator IP in Verilog HDL
- Help define and own ASIC design methodologies
- Lead cross functional SOC development activities
- Work with the different stakeholders and functional teams to ensure delivery of high quality IP to SoC product teams
- Provide technical leadership through personal example, mentorship, and strong teamwork
BASIC QUALIFICATIONS
- BS degree or higher in EE or CE or CS
- 5+ years or more of practical semiconductor ASIC design experience including owning end to end design of major SOC blocks
- Successful tape outs as an owner of a major design block
- Experience writing HDL in Verilog / SystemVerilog and understanding architectural models and algorithms in C / C++
- Proficient in design methodologies and EDA tools
- Experience working with Synthesis, timing and design constraints
PREFERRED QUALIFICATIONS
- In-depth knowledge of CPU, DSP, or programmable accelerators
- Experience working with RISC-V
- SOC bring-up and post silicon validation experience
- Experience with early power analysis
- Architecture / System engineering experience
- Experience developing with modern programming languages (Python, Java, C / C++), open-source technologies, and Linux.
- Experience with gate level testing and multi clock design practices (CDC)
- Experience working with software teams to tightly define the HW / SW interface including control / status registers, and error handling.
- Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.
- Experience in micro-architecture definition from architecture guideline and model analysis.
- Experience in RTL coding and debug, as well as performance / power / area analysis and trade-offs
- Experience in timing analysis and working with physical design teams to close timing.
- Experience in working with internal and external partners.
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