Search jobs > Santa Clara, CA > Temporary > Asic design engineer

ASIC/RTL Design Engineer - Senior (US)

Trilyon, Inc.
Santa Clara, CA, United States
Full-time
Quick Apply

For over 15 years, Trilyon has been at the forefront of providing comprehensive global workforce solutions and staffing services.

Leveraging our extensive expertise across multiple domains such as Cloud technology, Salesforce, AI, Machine Learning, and Technical Writing, we consistently exceed expectations in catering to a wide range of requirements.

Currently we are seeking a " ASIC / RTL Design Engineer " for one of our clients that is a leading multination corporation.

Role : ASIC / RTL Design Engineer

Location : : San Jose, CA

Type : Long Term Contract

Job Description :

  • Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.
  • Collaborate with architecture and hardware teams to understand the requirements.
  • Work with verification and physical design teams to achieve high quality design and successful tape out.
  • Design and implement logic functions that enable efficient test and debug.
  • Participate in silicon bring-up for features owned.
  • Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features.
  • Implement automation to increase design team efficiency.

PREFERRED EXPERIENCE :

  • 5-6+ years' experience
  • Must have proven track record of ASIC design on several production tape-outs.
  • Experience in Designing RTL block for an SOC.
  • Experience in integrating ASIC IP into an SOC.
  • Experience with Arm architecture and APB, AXI, CHI protocols.
  • Experience with synthesis, static timing analysis & optimizations.
  • Experience with design involving Interconnects.
  • Experience writing timing constraints and exceptions.
  • Experience with automation using scripting techniques such as PERL, Python or Tcl
  • Ability to develop clear and concise engineering documentation.
  • Experience in Power-saving techniques.
  • Ability to organize and present complex technical information.
  • Strong verbal and written communication skills

Sam Arora

Contact No. 408-834-7453

Email id- [email protected]

Equal Employment Opportunity

Trilyon is an Equal Opportunity Employer, committed to fairness and respect for all individuals. We value diversity in age, disability, ethnicity, gender, gender identity, religion, and sexual orientation, believing it drives innovation and better service.

Employment decisions are made impartially, without regard to any protected characteristic under federal, state, or local law.

Our diverse team drives innovation, competitiveness, and creativity, enhancing our ability to effectively serve our clients and communities.

This commitment to diversity makes us stronger and more adaptable.

1 day ago
Related jobs
Promoted
VirtualVocations
Fremont, California

A company is looking for a Senior ASIC Design Engineer responsible for digital SoC design and development. ...

Promoted
Antora Energy
San Jose, California

Bachelor's degree in Mechanical Engineering with 6+ years relevant industry experience OR Master's degree with 4+ years relevant industry experience OR Phd. You will collaborate with other teams to scope, define, design, model, prototype, validate, and iterate the mechanical design of Antora's therm...

Promoted
Fortinet
Sunnyvale, California

Fortinet is looking for a passionate ASIC Designer to join our R&D team! This role involves working on cutting edge high performance ASIC design from specification to RTL implementation. Design high performance and high quality ASIC/FPGA design from specification to RTL implementation. Strong track ...

Promoted
Sunlune
CA, United States

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gen...

Promoted
Mainspring Energy, Inc.
Menlo Park, California

Mainspring is seeking Senior Mechanical Engineers with a focus on designing hardware that requires thermal and fluids analysis. BS Degree in Mechanical Engineering or a similar engineering field from an accredited institution + 6 years of relevant industry experience or MS + 4 years of relevant indu...

Promoted
Apple Inc.
Cupertino, California

As an ASIC Design Engineer in the Pixel IP design team, you will work closely with many cross-functional teams (chip integration, physical design, power, logic design, and verification) to build high performance and low power pixel processing engines. In this front-end design role, your tasks will i...

Promoted
Nvidia Corporation
Santa Clara, California

Similar Jobs (5) Senior Physical Design Engineer locations US, CA, Santa Clara time type Full time posted on Posted 30+ Days Ago Senior Design Engineer locations US, CA, Santa Clara time type Full time posted on Posted 30+ Days Ago Senior Design Engineer locations US, CA, Santa Clara time type Full ...

Promoted
Apple Inc.
Cupertino, California

Are you a leader? Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? We have an extraordinary opportunity for senior level engineers to drive and lea...

BMW (US) Holding Corp.
Silicon Valley, California

They will be actively working with various internal teams engineering the architecture and design of new use cases and features. The Senior Systems Engineer creates Specifications for new products, services, and functionalities and secure fundamental IPR to solve such use cases. The Senior System En...

Annapurna Labs (U.S.) Inc.
Cupertino, California

We’re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. As a key member of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve ...