Job Description
Role : ASIC Physical Design Engineer
Work Location : San Francisco, CA / Santa Clara, CA
Interview : Phone / Skype
Job Type : Contact / W2
Job Responsibility
- Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO generation.
- Expertise in timing closure (STA) of high frequency blocks
- Handling blocks of high instance counts and complex designs 1M+ instances and clock frequencies about 1 GHz
- Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge.
- Experience in Block-level and Full-chip integration.
- Knowledge of signoff closure Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level
- Understanding constraints and fixing design / timing techniques
- Block level implementation from netlist to GDS
- Understanding SI prevention, fixing methodology and implementation
- Proficient in layout edit techniques
- Proficient in Synopsys Fusion Compiler, ICC / ICC2, PTSi, and Cadence EDA Tool Suite
- Experience in Design Automation and UNIX system.
- Experience in Tcl / Tk, PERL, Python is a plus.
Desired Skills & Experience :
- Must possess 8+ years of hands-on experience in handling block / chip level implementation from Netlist to GDSII
- Must possess hands on experience in timing closure and physical verification closure
- Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz
- Experience in handling lower tech nodes that include 3nm, 5nm, 7nm, 10nm, 16nm, etc.
- Must have hands on tape-out experience in lower tech nodes in any of the tools mentioned such ICC / ICC2, Fusion Compiler or Cadence APR tools.
- Must have the ability to think on the spot for quick solutions and work-around at the time of tape-out to hit the schedule on time
- Must possess excellent scripting skills TCL or Perl or Python
- Experience in Synthesis and Formal is a plus
- Excellent verbal and written communication skills are required.
- Must possess excellent debug skills, analytical skills, and the ability to work independently.
- Must be highly motivated and possess excellent team spirit
Synopsys Or Cadence EDA Tool Suite, STA, PrimeTime-Si, PNR,
Synopsys Or Cadence EDA Tool Suite, STA, PrimeTime-Si, PNR, Python / TCL
Additional Information
All your information will be kept confidential according to EEO guidelines.
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