ResponsibilitiesAbout ByteDanceFounded in 2012, ByteDance's mission is to inspire creativity and enrich life. With a suite of more than a dozen products, including TikTok, Helo, and Resso, as well as platforms specific to the China market, including Toutiao, Douyin, and Xigua, ByteDance has made it easier and more fun for people to connect with, consume, and create content.
Why Join UsCreation is the core of ByteDance's purpose. Our products are built to help imaginations thrive. This is doubly true of the teams that make our innovations possible.
Together, we inspire creativity and enrich life - a mission we aim towards achieving every day. To us, every challenge, no matter how ambiguous, is an opportunity;
to learn, to innovate, and to grow as one team. Status quo? Never. Courage? Always. At ByteDance, we create together and grow together.
That's how we drive impact - for ourselves, our company, and the users we serve. Join us. About the TeamOur team plays a crucial role in ensuring the company’s success.
We seek people who are willing to learn and put in the effort to solve problems. Our challenges are not your regular day-to-day problems - you’ll be part of a team that’s developing new solutions to new challenges.
It’s working fast, at scale, and we’re making a difference. We are looking for talents to join us on this exciting journey! Responsibilities- Architect and develop block-level SoC verification environment using SystemVerilog (SV) and Universal Verification Methodology (UVM).
- Write verification test plan and test objects for block / subsystem in ASICs.- Work closely with RTL (Register Transfer Level) designers to debug and root cause test failures and resolve design bugs.
- Analyze code coverage in block-level to determine how much RTL has been exercised / covered by test.- Develop functional coverage monitors to measure features / functions of the design have been exercised by the test suite.
- Perform gate level simulations to verify the correctness of netlist.- Influence the engineering culture of the product teams and advocating engineering excellence.
- Mentor Jr. Design Verification Engineers.QualificationsQualificationsMust have a Master's degree in Computer Science, Information Technology, Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field, and 5 years of related work experience;
OR a Bachelor's degree in Computer Science, Information Technology, Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field, and 7 years of related work experience, out of which 5 years must be post-bachelor's, progressive related work experience.
- Of the required experience, must have 5 years of experience in each of the following : - Architecting and developing block-level and chip-level verification environments using SystemVerilog and UVM methodology;
- Writing verification test plans for blocks / subsystems-level in the ASIC design, and developing code and functional coverage to measure what features and functionalities of the design specified in the functional spec have been exercised by the test suite;
- Developing and maintaining System C and C++ reference models for block-level verification environments;- Developing Perl, Python, and Shell scripts to improve verification infrastructure and methodology;
- Using front-end simulator tools VCS, NCverilog, Xcelium, or Verdi for block simulation, subsystem simulation, and full-chip simulations;
and- Using Xcelium or Verdi for waveform viewing and debugging the potential RTL issue. Type : Full time, 40 hours / weekLocation : San Jose, CASalary Range : $226325 - $355000 per year To
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