is looking for a digital verification engineer who is passionate about delivering differentiated low-power and battery-free wireless connectivity solutions.
Job title and responsibilities commensurate with experience.
Responsibilities :
- Develop test plans and verification infrastructure for low-power ASIC designs
- Build verification environments using SV / UVM methodology
- Build reusable bus functional models, drivers, monitors, checkers and scoreboards
- Debug / triage automated regressions, run gate level simulations, and perform coverage analysis
Requirements :
- Proficiency in verification test planning, test bench architecture, assertions, problem solving and debugging Constrained random verification experience with System Verilog using OVM or UVMSet up coverage driven verification (code / functional / assertion coverage)
- Strong knowledge of Verilog or VHDL
- BS or MS (preferred) degree in EE or equivalent, with 5+ years of experience
Nice to Have :
- Experience in testbenches (block, system) and setting up verification flow from ground-up
- Understands secure / non-secure, interrupts, memory, and clock frequency switching
- Familiar with low-power designs, understands power saving techniques and verifications
- Wireless communications, knowledge of BLE at the protocol level
Location :
- Campbell (Silicon Valley), California, USA
- Irvine, California, USA
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