Summary :
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly.
Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here.
The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it.
Join us to help deliver the next groundbreaking Apple product!We are seeking a seasoned Physical Design technical leader with deep expertise in high-performance & low-power design.
In this highly visible role, you will work closely with cross-functional teams to come up with efficient chip and IP physical architecture taking into account physical design constraints early in the design cycle.
Key Qualifications :
Minimum BS and 10+ years of relevant industry experience.Recent successful tapeouts in deep submicron technology. Knowledgeable in partition level P&R implementation including floorplanning, clock & power distribution, timing closure, and physical & electrical verification.
Strong knowledge of PD construction & analysis flows and methodology. Shown ability to execute to stringent schedule & die size requirements.
Strong interpersonal skills.Experienced in industry standard tools and understanding their capabilities and underlying algorithms.
Experience with large SOC designs (>
20M gates) with frequencies in excess of 1GHZ.
Description :
- You will be responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump / RDL, STA, physical verification, EMIR, sign-off.
- You will also collaborate to drive methodologies and "best-known methods" to streamline PD work and develop guidelines and checklists.
- You will be the primary technical contact for your focus area and are motivated to solve more challenging timing closure issues, area & power optimization etc.
Additional Requirements :
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