The selected candidate will be responsible for FPGA verification using the UVM methodology and following the Space processes.
IN THIS ROLE, YOU WILL :
- Work with low SWaP, radiation hardened, space rated devices.
- Devise a unique verification plan for a given design.
- Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment.
- Develop requirements, test cases, build test benches, generate reports, and document verification results.
- Work with an independent design team to document and resolve bugs found in the design.
- Support all aspects of ASIC and FPGA development, to include architecture, design, and analysis.
- Support technical reviews, and be able to present to internal and external stakeholders.
YOU WILL HAVE :
- Experience with UVM verification methodology
- Experience developing test cases based off given requirements.
- Experience building test benches for FPGA / ASIC designs to provide randomized stimulus.
- Experience identifying and implementing necessary test exclusions.
- Experience generating coverage reports (code and functional)
Hands on experience with UVM and closing functional and code coverage is required for this role.
Level 4 : BS 11 YRS or MS 9 YRS
Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.
FPGA Verification Engineer - Remote (Secret)
The selected candidate will be responsible for FPGA verification using the UVM methodology and following the *** Space processes. Devise a unique verification plan for a given design. Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance ...
FPGA Verification Engineer - UVM
Job Title: FPGA Verification Engineer - UVM. Evaluate current VCRM for Simulation verification and update the VCRM based on baselined FPGA requirements. The Simulation Verification phase includes design, development, and delivery of the following:. Evaluate current FW test methods for verification a...
FPGA Verification Engineer - Secret Clearance (Remote)
The selected candidate will be responsible for FPGA verification using the UVM methodology. Devise a unique verification plan for a given design. Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment. Develop require...
FPGA Design/Verification Engineer
The candidate will work across disciplines with Software Engineers and other ASIC/FPGA engineers to create leading edge products for future business growth. Position is for an ASIC/FPGA Engineer and will be responsible for ASIC & FPGA development on a R&D program. The candidate will have experience ...
Engineering - FPGA Design/Verification Engineer
Job Description: The selected candidate will be responsible for FPGA verification using the UVM methodology and following the Space processes. Devise a unique verification plan for a given design. Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high...
FPGA Design/Verification Engineer
Devise a unique verification plan for a given design. Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment. Develop requirements, test cases, build test benches, generate reports, and document verification results. ...
FPGA Design Verification Engineer
FPGA Design/Verification Engineer . The selected candidate will be responsible for FPGA verification using the UVM methodology and following the client Space processes. Devise a unique verification plan for a given design. Use SystemVerilog and Universal Verification Methodology (UVM) to verify a de...
FPGA Design/Verification Engineer
FPGA Design/Verification Engineer. The selected candidate will be responsible for FPGA verification using the UVM methodology and following the company processes. Devise a unique verification plan for a given design. Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design i...
SLD Electrical Power Systems - FPGA Verification Engineer III - Lunar Permanence
As an FPGA Verification Engineer working on avionics systems, you will need to possess a range of skills and experience to ensure the safe and reliable operation of critical systems. Understand design requirements and specifications in coordination with systems engineering, hardware engineering, sof...
Systems Engineer - IT, Sr / Linux / Clearance / Onsite - CO - Security Clearance Required
As a Linux System Engineer for the enterprise WAN solution, DarkStar, you'll be responsible for:. Supporting Multi Level Security systems (computation and storage), software, scheduling, and research applications. Experience with Trusted Multi-Level Security (MLS) Operating Systems. ...