Job Description
Role Overview
- Current state of the art testbench development such as UVM methodology
- Experience in design verification with UVM and System Verilog is a MUST
As a Design Verification Engineer, you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems.
Responsibilities
- Triage regression failures and make testbench updates
- Debug functional errors in RTL model using simulation and debug tools.
- Maintain efficient and clean regression status
- Develop Scalable System Verilog / UVM testbenches for unit level and / or Cluster level verification.
- Review Architecture and Micro-Architecture specifications.
- Closely work with Architects and RTL designers.
- Define, maintain and execute unit level and / or Cluster level verification test plans.
- Generate and run Testcases on logic simulation models.
- Code Functional coverage models and System Verilog assertions.
- Drive Functional Coverage and Code coverage to closure.
- Integrate C++ reference model into Scoreboards
Requirements
- 5-15 year’s industry experience in a design verification role.
- Proficient in System Verilog / UVM / OVM, OOP / C++
- Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
- Experience with code coverage and functional coverage driven verification methodology.
- Experience in creating, running and debugging of System Verilog / UVM constraint-random Testbench.
- Excellent working knowledge of scripting languages such as Python or Perl.
- Understanding of micro-architecture, logic design, FSMs, arithmetic data path pipelines.
- Strong functional verification experience including Test planning, Testbench Architecture, Test / Coverage Model / Assertion Development.
- Strong debugging skills
- Strong programming skills with good understanding of algorithms and data structures
Good verbal and written communication skills
Design Verification Engineer
Our work ranges from rescuing projects struggling with verification, through sophisticated verification IP development, to complete methodology engineering. BSc/MSc in Electronic Engineering, Computer Engineering, or Computer Science. Formal Verification: Formal Property Verification, Proof Kits. We...
Design Verification Engineer - Emulation
You will collaborate with architecture, design, verification, and software/firmware teams to develop emulation models and capabilities for various use cases such as functional verification, performance testing, software/firmware bring-up, running realistic workloads, power estimation, hybrid-simulat...
Design Verification Engineer
Experience in pre-silicon RTL Verification /IP Verification / SOC verification Strong knowledge of System Verilog and working knowledge of recent verification methodologies (UVM). Domain expertise in one or more of the following areas System-on-a-chip verification with multiple CPUs and fixed functi...
Sr Design Verification Engineer
Job Title: Sr Design Verification Engineer. Building on your background of Design Verification, RTL coding and IP Integration. Join the growing Encore Semi Front-End Development team to design and verify ASICs and SoCs targeting next generation applications. As a DV Engineer you will work with the t...
Cellular SOC Design Verification Engineer - Entry Level
As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state-of-the-art Cellular SoCs! You will have the opportunity to contribute to the verification effort of a set of complex SOCs ...
Design Verification Engineer
As our ASIC Product Engineer, you will work closely with other engineering disciplines as the design takes shape at the IP, SOC, and system level to ensure the final ASIC achieves program goals. We are looking for an experienced and results oriented Design Verification Engineer to join Ericsson's AS...
Sr. ASIC Design Verification Engineer
Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM, System C and DPI-C. Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models. Run formal verifica...
Senior Design Verification Engineer (SystemVerilog UVM)
Senior Design Verification Engineer. Experience with full verification flow including coverage closure. System verification (C based) experience. ...
Design Verification Engineer
Must possess a BS in Electrical Engineering, Computer Engineering, Computer Science or similar field with 3+ years of experience OR MS in Electrical Engineering, Computer Engineering, Computer Science or similar field with 2+ years' experience. This position is an IP Verification Engineering role on...
Senior Design Verification Engineer - Memory Subsystem Verification, C++, System Verilog
Are you looking to take on and tackle advanced engineering challenges? We are looking for open minded, flexible, innovative, and creative Engineers looking to join a new team to develop an end to end verification solution from IP/subsystem verification through advanced technics, including BIOS verif...