Job Description
PD implementation for a complex hierarchical subsystem in 4nm technology . Responsible for implementation & delivery of sub system and sub HM’s from netlist to GDS II .
Need hands-on on experience in place and route, timing and signoff of the entire subsystem. EDA Tools like FC compiler, Innovus, primetime , calibre etc.
Responsibility includes
- Physical Design engineer with proficiency in Innovus and FC to execute PnR of Complex blocks in advance technologies. Requires full exposure to all aspects of design flows like floor planning, placement, CTS, routing, crosstalk avoidance, physical verification (DRC / LVS), PDN, Timing Closure and power optimization.
- Well versed with timing, PnR and PV closure, methodologies, and flow automation for better PPA and predictable convergence.
- Good understanding of clocking architecture.
- Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
- Well versed with Tcl / Perl Scripting
- Well versed of Unix command and system.
- Strong problem-solving skills and good communication skills.
- Should have good exposure to high frequency multi voltage design convergence.
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