Senior/Principal DRAM Design Engineer - TPG

Micron Memory Malaysia Sdn Bhd
Boise, Idaho, US
Full-time

Our vision is to transform how the world uses information to enrich life for all .

Do not wait to apply after reading this description a high application volume is expected for this opportunity.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Job Responsibilities

As a Senior or Principal Lead DRAM Design Engineer, you will play a crucial role in the design and development of next-generation DRAM products.

Working collaboratively with various teams, including process integration, product engineering, and production design, you will contribute to the pathfinding of future DRAM nodes and bring groundbreaking insights to production.

Your deep understanding of array parasitic, speed / timing bottlenecks, and CMOS gate variability will drive design optimization and innovations, ensuring exceptional die size, quality, reliability, and power.

In this role, you will have the unique opportunity to lead a team known for their exceptional work, driving strategic goals, mentoring team members, and collaborating with partner teams to resolve issues.

Your technical expertise and effective communication will be key to successfully implementing the team's goals and delivering world-class DRAM products!

Required :

5+ Years DRAM Design experience

Education & Experience Necessary for Success

Bachelor's of Science in Electrical Engineering or Master's of Science in Electrical Engineering degree

Successful candidates for this position will also have :

  • Proficiency with UNIX and CADENCE design environment (Simulation, Schematic entry, SPF extraction)
  • Using Spice and Verilog, simulate to verify proper circuit operation. Analyze circuits for power consumption, speed performance, and reliability.
  • Experience with circuit verification and optimization including layout verification and parasitic extractions of the circuits
  • Model layout parasitic in the simulation and verify proper signal routing and power supply connections.
  • Create floorplans that optimize for the best circuit placement, signal routing, and power delivery.
  • Strong communication skills with the ability to convey complex technical concepts to other design peers both verbally and written.
  • A self-motivated, hard-working team player who enjoys working with diverse abilities and backgrounds.
  • Excellent problem-solving and analytical skills.

Preferred but not required

  • Experience inside memory industry of either flash, SRAM or DRAM, a plus
  • Experience in full-custom design and layout.
  • Possessing management experience or formal training in team leadership, a plus.
  • Experience with python (or other scripting language), a plus.

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1 day ago
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